END IF; END PROCESS; END A;
暂存器、通用寄存器、地址寄存器LS273:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS273 IS PORT(
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END LS273;
ARCHITECTURE A OF LS273 IS BEGIN
PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1') THEN O<=D; END IF; END PROCESS; END A;
1：2分配器FEN2：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY FEN2 IS PORT(
X:IN STD_LOGIC_VECTOR(7 DOWNTO 0); WR,LED_B:IN STD_LOGIC;
W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END FEN2;
ARCHITECTURE A OF FEN2 IS BEGIN
PROCESS(LED_B,WR) BEGIN
IF(LED_B='0' AND WR='0') THEN W2<=X; ELSE W1<=X; END IF; END PROCESS;
END A;
3选1数据选择器MUX3：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX3 IS PORT(
ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SW_B,CS:IN STD_LOGIC;
N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0); EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END MUX3;
ARCHITECTURE A OF MUX3 IS BEGIN
PROCESS(SW_B,CS) BEGIN
IF(SW_B='0') THEN EW<=ID;
ELSIF(CS='0')THEN EW<=N2; ELSE
EW<=N1; END IF; END PROCESS; END A;
5选1数据选择器MUX5：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX5 IS PORT(
C,D,E,F,G: IN STD_LOGIC;
X1,X2,X3,X4,x5: IN STD_LOGIC_VECTOR(7 DOWNTO 0); W: out STD_LOGIC_VECTOR(7 DOWNTO 0) );
END MUX5;
ARCHITECTURE A OF MUX5 IS
SIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
SEL<=G&F&E&D&C; PROCESS(SEL)
BEGIN
IF(SEL=\ W<=X1;
ELSIF(SEL=\ W<=X2;
ELSIF(SEL=\ W<=X3;
ELSIF(SEL=\ W<=X4;
ELSIF(SEL=\ W<=X5; ELSE
null; END IF; END PROCESS; END A;
程序计数器PC：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PC IS PORT(
load,LDPC,CLR: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END PC;
ARCHITECTURE A OF PC IS
SIGNAL QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(LDPC,CLR,load) BEGIN
IF(CLR='0') THEN QOUT<=\
ELSIF(LDPC'EVENT AND LDPC='1') THEN IF(load='0') THEN
QOUT<=D; --BUS->PC ELSE
QOUT<=QOUT+1; --PC+1 END IF; END IF;
END PROCESS; O<=QOUT; END A;
ROM芯片ROM16：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ROM16 IS PORT(
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CS:IN STD_LOGIC );
END ROM16;
ARCHITECTURE A OF ROM16 IS BEGIN
DOUT<=\ \
\ \ \ \ \
\ \ \ \ \
\ \ \ \ \ \END A;
时序产生器COUNTER： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS PORT(
Q,CLR: IN STD_LOGIC;
T1, T2,T3,T4: OUT STD_LOGIC );
END COUNTER;
ARCHITECTURE A OF COUNTER IS
SIGNAL X: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
PROCESS(Q,CLR) BEGIN
IF(CLR='0') THEN T1<='0'; T2<='0'; T3<='0'; T4<='0'; X<=\
ELSIF(Q'EVENT AND Q='1') THEN X<=X+1;
T2<=(NOT X(1)) AND X(0); T3<=X(1) AND (NOT X(0)); T4<=X(1) AND X(0); END IF; END PROCESS; END A;
各个器件生成后，开始用自己设计的指令编写汇编程序，程序如下所示： MOV R1,0 ;寄存器R1用来存放最后的结果
MOV R2,0 ;寄存器R2放了一个立即数0，用来做是否负数判读以及做输入是 ;否达到5次的比较标准
MOV R3,5 ;记录输入次数，从5开始递减 INPUT:
IN1 R0 ;寄存器R0用来存放输入的数据
DEC R3 ;每输入一次则R3递减1，递减到0说明刚好输入5个数据 CMP R0,R2 ;判断输入的数据是否是负数 JB L1 ;如果是负数，则转到标号L1执行
CMP R2,R3 ;如果不是负数，则判断输入是否够5次 JB INPUT ;若不够5次则跳转到INPUT JMP L2 ;若够5次就跳转到L2执行 L1:
MUL R0,R0 ;负数球平方和
ADD R0,R1 ;求得的平方放入R1中 CMP R2,R3 ;比较是否够5次输入
计算机组成原理课程设计论文
