Readback Command Sequences
Accessing Configuration Registers through the JTAG Interface
JTAG access to the Spartan-6 FPGA configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like BYPASS and
BOUNDARY_SCAN. Data shifted into the CFG_IN register goes to the configuration packet processor, where it is processed in the same way commands from the SelectMAP interface are processed.
Readback commands are written to the configuration logic by going through the CFG_IN register; configuration memory is read through the CFG_OUT register. The JTAG state transitions for accessing the CFG_IN and CFG_OUT registers are described in Table6-4.
Table 6-4:Step
1234
Shifting in the JTAG CFG_IN and CFG_OUT Instructions
Description
Set and HoldTDI
XXXX000101 (CFG_IN)000100 (CFG_OUT)
0XXX
TMS
1010
# of Clocks (TCK)
5122
Clock five 1s on TMS to bring the device to the TLR stateMove into the RTI stateMove into the Select-IR stateMove into the Shift-IR state
Shift the first five bits of the CFG_IN or CFG_OUT instruction, LSB first
Shift the MSB of the CFG_IN or CFG_OUT instruction while exiting SHIFT-IR
Move into the SELECT-DR stateMove into the SHIFT-DR state
Shift data into the CFG_IN register or out of the CFG_OUT register while in SHIFT_DR, MSB first
505
6789
1100
122X
1011
Shift the LSB while exiting SHIFT-DRReset the TAP by clocking five 1s on TMS
XX
11
15
Configuration Register Read Procedure (JTAG)
The simplest read operation targets a configuration register such as the COR0 or STAT register. Any configuration register with read access can be read through the JTAG
interface, although not all registers offer read access. The procedure for reading the STAT register through the JTAG interface follows:1.2.
Reset the TAP controller.
Shift the CFG_IN instruction into the JTAG Instruction Register through the Shift-IRstate. The LSB of the CFG_IN instruction is shifted first; the MSB is shifted whilemoving the TAP controller out of the SHIFT-IR state.
Shift packet write commands into the CFG_IN register through the Shift-DR state:a.b.c.
Write the synchronization word to the device.
Write the read STAT register packet header to the device.
Write two dummy words to the device to flush the packet buffer.
3.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
CRC Masking
CLB with LUT Configured as Distributed RAM or Shift Register
Only the SLICEM contains LUTs capable of being configured as distributed RAM. The architecture of Spartan-6FPGAs pairs a SLICEM with a SLICEX in a CLB alternating with a CLB comprised of a SLICEL with a SLICEX. For more information on CLB composition, see UG384, Spartan-6FPGA Configurable Logic Block User Guide. A frame of data spans 16CLBs, which includes 64 LUTs. For simplification, LUT6 (created using two LUT5 components) are shown in Figure8-1 to demonstrate the frame data association with the CLB.
X-Ref Target - Figure 8-1Segments of four frames shown passing throughthe LUTs of the two SLICEMs within a CLBLUT6LUT6LUT6LUT6LUT6LUT616 CLBsLUT6SLICEM FramesLUT6SLICEX FramesSLICEMSLICELSLICEXCLBCLBUG380_c8_01_052412Figure 8-1:CLB Frame Masking with Distributed RAM
There are two types of CLBs, those containing SLICEM, which are able to configure as distributed RAM, and those containing SLICEL, which cannot. SLICEM CLBs are the only type that are masked in this scenario.
When a single LUT is configured as a distributed RAM, the 15 adjacent CLBs sharing the same frame must be masked. Consequently, to maximize coverage of the CRC, it is
recommended to constrain LUTs configured as distributed RAM to frame boundaries. This limits the amount of masking performed by BitGen and therefore increases the CRC coverage.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2V80-4BG728I中文规格书
