AIIGX51006-4.2
This chapter describes how Arria? II devices provide I/O capabilities that allow you to work in compliance with current and emerging I/O standards and requirements. With these device features, you can reduce board design interface costs and increase development flexibility.
Package and die enhancements with dynamic termination and output control provide best-in-class signal integrity. Numerous I/O features assist high-speed data transfer into and out of the device, including:
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Single-ended, non-voltage-referenced, and voltage-referenced I/O standardsLow-voltage differential signaling (LVDS), reduced swing differential signal(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTLBus LVDS (BLVDS) for Arria II GX devicesProgrammable output current strengthProgrammable slew rateProgrammable bus-holdProgrammable pull-up resistorOpen-drain output
On-chip series termination (RS OCT)On-chip differential termination (RD OCT)
On-chip parallel termination (RT OCT) for Arria II GZ devicesDynamic OCT for Arria II GZ devicesProgrammable pre-emphasis
Programmable voltage output differential (VOD)“I/O Standards Support” on page6–2“I/O Banks” on page6–5“I/O Structure” on page6–10“OCT Support” on page6–19
“Arria II OCT Calibration” on page6–26
“Termination Schemes for I/O Standards” on page6–28“I/O Bank Restrictions” on page6–36
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This chapter includes the following sections:
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Arria II Device Handbook Volume 1: Device Interfaces and IntegrationDecember 2011
Chapter 6:I/O Features in Arria II Devices
I/O Standards Support
I/O Standards Support
Table6–1 lists the supported I/O standards for Arria II GX devices and the typical values for input and output VCCIO, VCCPD, VREF, and board VTT.
Table6–1.I/O Standards and Voltage Levels for Arria II GX Devices
Standard SupportJESD8-BJESD8-BJESD8-5JESD8-7JESD8-11JESD8-12PCI Rev 2.2PCI-X Rev 1.0JESD8-9BJESD8-15—JESD8-6JESD8-6JESD8-16AJESD8-9BJESD8-15—JESD8-6JESD8-6JESD8-16AANSI/TIA/EIA-644———
VCCIO (V)
I/O Standard
3.3-V LVTTL/3.3-V LVCMOS3.0-V LVTTL/3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVCMOS1.2-V LVCMOS3.0-V PCI3.0-V PCI-X (1)SSTL-2 Class I, IISSTL-18 Class I, IISSTL-15 Class I HSTL-18 Class I, IIHSTL-15 Class I, IIHSTL-12 Class I, IIDifferential SSTL-2Differential SSTL-18Differential SSTL-15 Differential HSTL-18Differential HSTL-15Differential HSTL-12LVDS
RSDS and mini-LVDSLVPECLBLVDS
Notes to Table6–1:
Input Operation3.3/3.0/2.53.3/3.0/2.53.3/3.0/2.5 1.8/1.51.8/1.51.23.03.0 (2)(2)(2)(2)(2)(2)(2), (3)(2), (3)(2), (3)(2), (3)(2), (3)(2), (3)(2)—(2)(2)
Output Operation3.33.02.51.81.51.23.03.02.51.81.51.81.51.22.51.81.51.81.51.22.52.5—2.5
VCCPD (V) 3.33.02.52.52.52.53.03.02.52.52.52.52.52.52.52.52.52.52.52.52.52.52.52.5
VREF (V) VTT (V)
————————1.250.750.900.750.6——————————
————————1.250.750.900.750.61.250.900.750.900.750.60————
0.90 0.90 (1)PCI-X does not meet the PCI-X I-V curve requirement at the linear region.
(2)Single-ended SSTL/HSTL, differential SSTL/HSTL, LVDS, LVPECL, and BLVDS input buffers are powered by VCCPD.(3)Differential SSTL/HSTL inputs use LVDS differential input buffers without RD OCT support.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 6:I/O Features in Arria II DevicesI/O Standards Support
Table6–2 lists the supported I/O standards for Arria II GZ devices and the typical values for input and output VCCIO, VCCPD, VREF, and board VTT.
Table6–2.I/O Standards and Voltage Levels for Arria II GZ Devices(Note1)(Part 1 of 2)
VCCIO (V)
I/O Standard
Standard Support
Input OperationColumn I/O Banks3.0/2.53.0/2.53.0/2.5 1.8/1.51.8/1.51.23.03.0(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)
Row I/O Banks 3.0/2.53.0/2.53.0/2.5 1.8/1.51.8/1.51.23.03.0(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)
Output OperationColumn I/O Banks3.03.02.5 1.8 1.51.23.03.02.51.81.51.51.81.51.51.21.22.51.81.51.51.81.51.51.21.2
Row I/O Banks3.03.02.5 1.8 1.51.23.03.02.51.81.5—1.81.5—1.2—2.51.81.5—1.81.5—1.2—
VCCPD (V) VREF (V) (Pre-(Input
Driver Ref Voltage)Voltage)3.03.02.52.52.52.53.03.02.52.52.52.52.52.52.52.52.52.52.52.52.52.52.52.52.52.5
————————1.250.900.750.750.900.750.750.60.6—————————
VTT (V)
(Board Termination Voltage)
————————1.250.900.750.750.900.750.750.60.61.250.900.750.750.900.750.750.600.60
3.3-V LVTTL3.3-V LVCMOS (3)2.5-V LVCMOS1.8-V LVCMOS1.5-V LVCMOS1.2-V LVCMOS3.0-V PCI3.0-V PCI-XSSTL-2 Class I, IISSTL-18 Class I, IISSTL-15 Class ISSTL-15 Class IIHSTL-18 Class I, IIHSTL-15 Class IHSTL-15 Class IIHSTL-12 Class IHSTL-12 Class IIDifferential SSTL-2 Class I, II
Differential SSTL-18 Class I, II
Differential SSTL-15 Class I
Differential SSTL-15 Class II
Differential HSTL-18 Class I, II
Differential HSTL-15 Class I
Differential HSTL-15 Class II
Differential HSTL-12 Class I
Differential HSTL-12 Class II
JESD8-BJESD8-BJESD8-5JESD8-7JESD8-11JESD8-12PCI Rev 2.1PCI-X Rev 1.0JESD8-9BJESD8-15——JESD8-6JESD8-6JESD8-6JESD8-16AJESD8-16AJESD8-9BJESD8-15——JESD8-6JESD8-6JESD8-6JESD8-16AJESD8-16A
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 6:I/O Features in Arria II Devices
I/O Standards Support
Table6–2.I/O Standards and Voltage Levels for Arria II GZ Devices(Note1)(Part 2 of 2)
VCCIO (V)
I/O Standard
Standard Support
Input OperationColumn I/O Banks(2)(2)(2)(4)
Row I/O Banks (2)(2)(2)2.5
Output OperationColumn I/O Banks2.52.52.5—
Row I/O Banks2.52.52.5—
VCCPD (V) VREF (V) (Pre-(Input
Driver Ref Voltage)Voltage)2.52.52.52.5
————
VTT (V)
(Board Termination Voltage)
————
LVDS (4), (5), (8)RSDS (6), (7), (8)mini-LVDS (6), (7), (8)LVPECL
Notes to Table6–2:
ANSI/TIA/EIA-644———
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 6:I/O Features in Arria II DevicesI/O Banks
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGZ300FF35I3N中文规格书 - 图文
