Chapter 5
【以下为老版教材（John F. Wakerly著）的题号】
6.16 Which CMOS circuit would you expect to be faster, a decoder with active-high outputs or one with active-low outputs?
6.20 Show how to build each of the following single- or multiple-output logic functions using one or more 74×138 or 74×139 binary decoders and NAND gates.
(Hint: Each realization should be equivalent to a sum of minterms.)
(a) F = (2,4,7)
?(c) F = ?(e) F = ∑
X,Y,ZA,B,C,D(0,2,10,12)
W,X,Y (0,2,4,5) G =
∑
W,X,Y (1,2,3,6)
6.21 What’s terribly wrong with the circuit in Figure 6-1? Suggest a change that eliminates the terrible problem.
Figure 6-1
6.43 Show how to build all four of the following functions using one SSI package and one 74×138. F1 = X'·Y'·Z' + X·Y·Z F2 = X'·Y'·Z + X·Y·Z' F3 = X'·Y·Z' + X·Y'·Z F4 = X·Y'·Z' + X'·Y·Z
6.50 Design a 10-to-4 encoder, with inputs in the 1-out-of-10 code and, outputs in a code like normal BCD except that input lines 8 and 9 are encoded into the hexadecimal digits \
6.52 Draw the logic diagram for a circuit that uses the 74x148 to resolve priority among eight active-high inputs, I0 ~ I7, where I7 has the highest priority. The circuit should produce active-high address outputs A2 ~ A0 to indicate the number of the highest-priority asserted input. If no input is asserted, then A2 ~ A0 should be 111 and IDLE ouput should be asserted. You may use discrete gates in addition to the ’148. Be sure to name all signals with the proper active levels.
6.53 Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, I0_L ~ I7_L, where I0_L has the highest priority. The circuit should produce active-high address outputs A2 ~ A0 to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to name all signals with the proper active levels. This circuit can be built with a single 74x148 and no other gates.
【电子科技大学】2015下数字逻辑设计(作业题)Chapter 5 Exercises(对应老教材第6章题号)
