FPGA可编程逻辑器件芯片EP2AGZ300HF40I3N中文规格书 - 图文

DLL

DQS phase-shift circuitry uses a DLL to dynamically control the clock delay required by the DQS/CQ and CQn pins. The DLL, in turn, uses a frequency reference to

dynamically generate control signals for the delay chains in each of the DQS/CQ and CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are Gray-coded to reduce jitter when the DLL updates the settings. Phase-shift circuitry requires a maximum of 1,280 clock cycles to lock and calculate the correct input clock period when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are required. Do not send data during these clock cycles because there is no guarantee that the data is properly captured. As the settings from the DLL may not be stable until this lock period has elapsed, be aware that anything with these settings may be unstable during this period.

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You can still use the DQS phase-shift circuitry for any memory interfaces that are operating at less than 100MHz. However, the DQS signal may not shift over 2.5ns. At less than 100MHz, while the DQS phase shift may not be exactly centered to the data valid window, sufficient margin must still exist for reliable operation.

There are two DLLs in an Arria II GX device and four DLLs in ArriaIIGZ device, located in the top-left and bottom-right corners of the ArriaIIGX device and each corner of the ArriaIIGZ device. These DLLs can support a maximum of two unique frequencies (ArriaIIGX devices) or four unique frequencies (ArriaIIGZ devices), with each DLL running at one frequency. Each DLL can have two outputs with different phase offsets, which allows one Arria II GX device to have four different DLL phase shift settings and ArriaIIGZ device to have eight different DLL phase shift settings.

For ArriaIIGX devices, each DLL can access the top, bottom, and right side of the device. This means that each I/O bank is accessible by two DLLs, giving more flexibility to create multiple frequencies and multiple-type interfaces. The DLL outputs the same DQS delay settings for the different sides of the device.

For ArriaIIGZ devices, each DLL can access the two adjacent sides from its location within the device. For example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B, 7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and 2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility to create multiple frequencies and multiple-type interfaces. You can have two different interfaces with the same frequency on the two sides

adjacent to a DLL, where the DLL controls the DQS delay settings for both interfaces.

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Interfaces that span across two sides of the device are not recommended for high-performance memory interface applications. However, Arria II GX devices support split interfaces (top and bottom I/O banks) and interfaces with multiple DQ/DQS groups wrapping over column and row I/Os from adjacent sides of the devices. Interfaces spanning “top and bottom I/O banks”, “right and bottom I/O banks”, or “top, bottom, and right I/O banks” are supported.

For ArriaIIGX devices, each bank can use settings from either one or both DLLs. For example, DQS1R can get its phase-shift settings from DLL0, and DQS2R can get its phase-shift settings from DLL1.

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Chapter 7:External Memory Interfaces in ArriaII Devices

Arria II External Memory Interface Features

For ArriaIIGZ devices, each bank can use settings from either or both adjacent DLLs the bank. For example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its phase-shift settings from DLL1.

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If you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to No Compensation or the QuartusII software automatically changes it. Because the PLL does not use any other outputs, it does not have to compensate for any clock paths.

Arria II devices support PLL cascading. If you cascade PLLs, you must use PLLs adjacent to each other (for example, PLL5 and PLL6 for ArriaIIGX devices) so that the dedicated path between the two PLLs is used instead of using a global clock (GCLK) or regional clock (RCLK) network that might be subjected to core noise. The TimeQuest Timing Analyzer takes PLL cascading into consideration for timing analysis.

Table7–5 lists the DLL location and supported I/O banks for ArriaIIGZ devices. Table7–5.DLL Location and Supported I/O Banks for ArriaIIGZ Devices

DLLDLL0DLL1DLL2DLL3

LocationTop-left cornerBottom-left cornerBottom-right cornerTop-right corner

Accessible I/O Banks (1)

1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C

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Note to Table7–5:

(1)The DLL can access these I/O banks if they are available for memory interfacing.

Table7–6 lists the reference clock for each DLL might come from PLL output clocks or dedicated clock input pins for ArriaIIGX devices. Table7–6.DLL Reference Clock Input for ArriaIIGX Devices

DLL

CLKIN(Top/Bottom)CLK12CLK13CLK14CLK15CLK4CLK5CLK6CLK7(Note1)

PLL

CLKIN(Right)

DLL0—CLK8CLK9CLK10CLK11PLL1

DLL1PLL3

Note to Table7–6:

(1)CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to CLK15are located on the top side of the device.

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 7:External Memory Interfaces in ArriaII DevicesArria II External Memory Interface Features

For ArriaIIGZ devices, the reference clock for each DLL may come from PLL output clocks or any of the two dedicated clock input pins located in either side of the DLL. Table7–7 through Table7–9 show the available DLL reference clock input resources for the ArriaIIGZ devices.

Table7–7.DLL Reference Clock Input for EP2AGZ300 and EP2AGZ350 Devices in the 780-Pin FineLine BGA Package

DLL

CLKIN (Top/Bottom)

CLK12P

DLL0

CLK13PCLK14PCLK15PCLK4P

DLL1

CLK5PCLK6PCLK7PCLK4P

DLL2

CLK5PCLK6PCLK7PCLK12P

DLL3

CLK13PCLK14PCLK15P

—

PLL_T2

—

—

—

PLL_B2

—

—

—

PLL_B1

—

—

—

PLL_T1

—

—

CLKIN (Left/Right)

PLL (Top/Bottom)

PLL (Left/Right)

PLL (Corner)

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 7:External Memory Interfaces in ArriaII Devices

Arria II External Memory Interface Features

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 7:External Memory Interfaces in ArriaII DevicesArria II External Memory Interface Features

Figure7–20 shows the DQS phase-shift circuitry for ArriaII devices. The input reference clock goes into the DLL to a chain of up to 16 delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. The phase comparator then issues the upndn signal to the

Gray-coded counter. This signal increments or decrements a 6-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase.

Figure7–20.Simplified Diagram of the DQS Phase-Shift Circuitry for ArriaII Devices

(Note1)

addnsubPhase offset settingsfrom the logic array( offset [5:0] )(offsetctrlout [5:0])DLL0 phase offsetsettings to top and rightside, DLL1 phase offsetsettings to bottom side ofthe device (3) 6DLLInput ReferenceClock (2)offsetdelayctrlout [5:0]aloadoffsetdelayctrlin [5:0]PhaseOffsetControl A6(dll_offset_ctrl_a)upndninclkPhaseComparatorupndninclkenaUp/DownCounteraddnsubPhase offset settingsfrom the logic array( offset [5:0] )6PhaseOffsetControl B(offsetctrlout [5:0])DLL0 phase offsetsettings to bottom side,DLL1 phase offset settings to right and top side of thedevice (3)offsetdelayctrlout [5:0]6Delay Chainsdelayctrlout [5:0]6offsetdelayctrlin [5:0]6(dll_offset_ctrl_b)DQS DelaySettings(4)6dqsupdateNotes to Figure7–20:

(1)All features of the DQS phase-shift circuitry are accessible from the UniPHY IP core and ALTMEMPHY megafunction in the QuartusII software.(2)The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input

clock pin, refer to Table7–6 and Table7–10.(3)Phase offset settings can only go to the DQS logic blocks.(4)DQS delay settings can go to the logic array and DQS logic block.

You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can capture the data properly.

Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, or 240°. The shifted DQS signal is then used as the clock for the DQ IOE input registers.

All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal phase shifted by a different degree amount but all must be referenced at one

particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60° phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift

combinations are supported. The phase shifts on the DQS pins referenced by the same DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), 45° (up to 180°), or 60° (up to 240°).

Arria II Device Handbook Volume 1: Device Interfaces and Integration