FPGA可编程逻辑器件芯片XC2S15-6FG456C中文规格书 - 图文

Chapter3

Boundary-Scan and JTAG Configuration

Introduction

Virtex?-5 devices support IEEE standards 1149.1 and 1532. IEEE 1532 is a standard for In-System Configuration (ISC), based on the IEEE 1149.1 standard. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to ensure the board-level integrity of individual components and the interconnections between them. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture is commonly referred to as JTAG. With multi-layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use, Boundary-Scan testing is becoming widely used as an important debugging tool.

Devices containing Boundary-Scan logic can send data out on I/O pins in order to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device-specific behavior. These tests are commonly used to detect opens and shorts at both the board and device level.

In addition to testing, Boundary-Scan offers the flexibility for a device to have its own set of user-defined instructions. The added common vendor-specific instructions, such as configure and verify, have increased the popularity of Boundary-Scan testing and functionality.

JTAG Configuration/Readback

Full Initial Configuration or Reconfiguration

1.2.3.4.5.6.7.8.

Load the JPROGRAM instruction into the JTAG Instruction Register (IR).

Loop on an Instruction Register load/capture with the CFG_IN instruction and waitfor the captured value of INIT_COMPLETE (bit 4 of IR capture) to be 1.Go to Shift-DR and load the new bitstream.Go to the Test-Logic-Reset state (TLR).Load the JSTART instruction into the JTAG IR.Go to Run-Test-Idle (RTI).Clock TCK for 12 cycles.

Load the CFG_IN instruction into the JTAG IR.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 3:Boundary-Scan and JTAG Configuration

9.

Go to Shift-DR and load the following bitstream fragment to read the ConfigurationSTATUS register:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0010 1000 0000 0000 1110 0000 0000 0001 // Type 1 header: Read 1 word

// from STAT

0000 0000 0000 0000 0000 0000 0000 0000 // flush pipeline

10.Load the CFG_OUT instruction into the JTAG IR.

11.Go to Shift-DR and shift out the STAT register data. Check that the crc_error (bit 0) is 0

and that the release_done (bit 13) is 1.12.Go to TLR.

Partial Reconfiguration

1.2.

Load the CFG_IN instruction into the JTAG IR.

Go to Shift-DR and load the following bitstream fragment to clear the CRC_ERRORsignal:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg0000 0000 0000 0000 0000 0000 0000 0111 // RCRC command0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0000 0000 0000 0000 0000 0000 0000 0000 // flush pipeline

3.4.5.6.7.

Load the JSHUTDWN instruction into JTAG IR.Go to Run-Test-Idle (RTI).

Clock TCK for 12 cycles to clock shutdown sequence (asserts GTS_CFG and deassertsGWE and DONE).

Load the CFG_IN instruction.

Go to Shift-DR and load the following bitstream fragment to assert the GHIGH_Bsignal:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg0000 0000 0000 0000 0000 0000 0000 1000 // AGHIGH command0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

8.9.

Load the reconfiguration bitstream.Go to TLR.

10.Load the JSTART instruction into the JTAG IR.11.Go to Run-Test-Idle (RTI).12.Clock TCK for 12 cycles.13.Go to Test-Logic-Reset (TLR).

Readback - Type 1: No Block RAM Frames

1.

Load the CFG_IN instruction into the JTAG IR.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

JTAG Configuration/Readback

2.

Go to Shift-DR and load the following bitstream fragment to write the RCFGcommand to the CMD register:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg0000 0000 0000 0000 0000 0000 0000 0100 // RCFG command

0011 0000 0000 0000 0010 0000 0000 0001 // Write 1 word to FAR

0000 0000 0000 0000 0000 0000 0000 0000 // Frame address: Top row 0/CLB

// Block Type/Column 0/Frame 0

0010 1000 0000 0000 0110 0000 0000 0000 // Type 1 header: Read FDRO 0100 1bbb bbbb bbbb bbbb bbbb bbbb bbbb // Type 2 header: Readback

// wordcount (27 bits) - CLB// frames only

0000 0000 0000 0000 0000 0000 0000 0000 // Flush pipeline

3.4.5.

Load the CFG_OUT instruction into the JTAG IR.Go to Shift-DR and shift out the readback data.Go to Test-Logic-Reset (TLR).

Readback - Type 2: Including Block RAM Frames

1.2.

Load the CFG_IN instruction into the JTAG IR.

Go to Shift-DR and load the following bitstream fragment to clear the CRC_ERRORsignal:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg0000 0000 0000 0000 0000 0000 0000 0111 // RCRC command0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0000 0000 0000 0000 0000 0000 0000 0000 // flush pipeline

3.4.5.6.7.

Load the JSHUTDWN instruction into the JTAG IR.Go to Run-Test-Idle (RTI).

Clock TCK for 12 cycles to clock the shutdown sequence (asserts GTS_CFG anddeasserts GWE and DONE).

Load the CFG_IN instruction into the JTAG IR.

Go to Shift-DR and load the following bitstream fragment to write the RCFGcommand to the CMD register:

1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP

0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg0000 0000 0000 0000 0000 0000 0000 0100 // RCFG command

0011 0000 0000 0000 0010 0000 0000 0001 // Write 1 word to FAR

0000 0000 0000 0000 0000 0000 0000 0000 // Frame address: Top row 0/CLB

// Block Type/Column 0/Frame 0

0010 1000 0000 0000 0110 0000 0000 0000 // Type 1 header: Read FDRO0100 1bbb bbbb bbbb bbbb bbbb bbbb bbbb // Type 2 header: Readback

// wordcount (27 bits) - CLB// and Block RAM frames

0000 0000 0000 0000 0000 0000 0000 0000 // Flush pipeline

8.Load the CFG_OUT instruction into the JTAG IR.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 5:Dynamic Reconfiguration Port (DRP)

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020