AD7705/AD7706
On the AD7706, the voltages applied to the analog input
channels are referenced to the COMMON input. For example, if AIN1(?) is 2.5 V and AD7705 is configured for unipolar
operation with a gain of 2 and a VREF of 2.5 V, the input voltage range on the AIN1(+) input is 2.5 V to 3.75 V.
If AIN1(?) is 2.5 V and AD7705 is configured for bipolar mode with a gain of 2 and a VREF of 2.5 V, the analog input range on the AIN1(+) input is 1.25 V to 3.75 V (i.e., 2.5 V ± 1.25 V). If AIN1(?) is at GND, the part cannot be configured for bipolar ranges in excess of ±100 mV.
Bipolar or unipolar options are chosen by programming the B/U bit of the setup register. This programs the channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change the input signal conditioning, it simply changes the data output coding and the points on the transfer function where calibrations occur.
Recommended reference voltage sources for the AD7705/ AD7706 with a VDD of 5 V include the AD780, REF43, and REF192; the recommended reference sources for the AD7705/ AD7706 operated with a VDD of 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references to reduce the noise level further.
DIGITAL FILTERING
The AD7705/AD7706 each contain an on-chip, low-pass digital filter that processes the output of the Σ-Δ modulator. Therefore, the parts not only provide the ADC function, but also provide a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain, rather than in the analog domain.
For example, because it occurs after the A/D conversion
process, digital filtering can remove noise injected during the conversion process, whereas analog filtering cannot do this. In addition, the digital filter can be made programmable far more readily than the analog filter. Depending on the digital filter design, this provides the user with the update rate.
On the other hand, analog filtering can remove noise
superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits.
To alleviate this problem, the AD7705/AD7706 have overrange headroom built into the Σ-Δ modulator and digital filter that allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consider filtering the analog input, or reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This provides an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%).
In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenuated bands occur around multiples of the sampling frequency, fS, as defined in Table 23. Thus, the unattenuated bands occur at n × fS (where n = 1, 2, 3 . . .). At these frequencies, there are frequency bands ±f3 dB wide (f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output.
REFERENCE INPUT
The AD7705/AD7706 reference inputs, REF IN(+) and REF IN(?), provide a differential reference input capability. The common-mode range for these differential inputs is from GND to VDD. The nominal reference voltage, VREF (REF IN(+) ? REF IN(?)), for specified operation is 2.5 V for the AD7705/AD7706 operated with a VDD of 5 V, and 1.225 V for the AD7705/AD7706 operated with a VDD of 3 V. The parts are functional with VREF voltages down to 1 V, but performance will be degraded because the output noise, in terms of LSB size, is larger. REF IN(+) must be greater than REF IN(?) for correct operation of the AD7705/AD7706. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ±1 nA over temperature, and source resistance might result in gain errors on the part. In this case, the sampling switch resistance is 5 kΩ typ, and the reference capacitor, CREF, varies with gain. The sample rate on the reference inputs is fCLKIN/64 and does not vary with gain. For gains of 1 and 2, CREF is 8 pF; for gains of 16, 32, 64, and 128, it is 5.5 pF, 4.25 pF, 3.625 pF, and 3.3125 pF, respectively.
The output noise performance outlined in Table 5, Table 6, Table 7, and Table 8 is for an analog input of 0 V, which effectively removes the effect of noise on the reference. To
obtain the noise performance shown in the noise tables over the full input range requires a low noise reference source for the AD7705/AD7706. If the reference noise in the bandwidth of interest is excessive, it degrades the performance of the
AD7705/AD7706. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage is removed because the application is ratiometric.
Rev. C | Page 23 of 44
AD7705/AD7706
Filter Characteristics
The AD7705/AD7706 digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for the filter is described in the z-domain by
H(z)
11?Z×
N1?Z?1
?N
3
0–20–40–60–80GAIN (dB)3
–100–120–140–160and in the frequency domain by
H(f)=
1sin(N×π×f/fS)×Nsin(π×f/fS)–180–200–220–240060120180240FREQUENCY (Hz)30036001166-015where N is the ratio of the modulator rate to the output rate. The phase response is defined by the following equation:
∠H=?3π(N?2)×ffSRad
Figure 15 shows the filter frequency response for a cutoff
frequency of 15.72 Hz, which corresponds to a first filter notch frequency of 60 Hz. The plot is shown from dc to 390 Hz. This response is repeated at either side of the digital filter’s sample frequency and at either side of multiples of the filter’s sample frequency.
The response of the filter is similar to that of an averaging filter, but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for Figure 15, where the output rate is 60 Hz, the first notch of the filter is at 60 Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches.
The cutoff frequency of the digital filter is determined by the value loaded to Bit FS0 and Bit FS1 in the clock register. Programming a different cutoff frequency via Bit FS0 and Bit FS1 does not alter the profile of the filter response, but changes the frequency of the notches. The output update of the part and the frequency of the first notch correspond.
Because the AD7705/AD7706 contain this on-chip, low-pass filtering, a settling time is associated with step function inputs, and data on the output is invalid after a step change until the settling time has elapsed. The settling time depends on the output rate chosen for the filter. The settling time of the filter to a full-scale step input can be up to four times the output data period. For a synchronized step input using the FSYNC function, the settling time is three times the output data period.
Figure 15. Frequency Response of AD7705 Filter
Postfiltering
The on-chip modulator provides samples at a 19.2 kHz output rate with fCLKIN at 2.4576 MHz. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the programmed output rate of the filter. Because the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth satisfies most application requirements. Some applications, however, might require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate will require postfiltering following the digital filtering performed by the AD7705/AD7706.
For example, if the required bandwidth is 7.86 Hz, but the required update rate is 100 Hz, data can be taken from the AD7705/AD7706 at the 100 Hz rate, giving a ?3 dB bandwidth of 26.2 Hz. Postfiltering can then be applied to reduce the bandwidth and output noise to the 7.86 Hz bandwidth level while maintaining an output rate of 100 Hz.
Postfiltering can also be used to reduce the output noise from the devices for bandwidths below 13.1 Hz. At a gain of 128 and a bandwidth of 13.1 Hz, the output rms noise is 450 nV. This is essentially device noise, or white noise. Because the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 13.1 Hz, the noise in the resultant pass band is reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering results in a longer settling time.
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半导体传感器AD7694BRMZ中文规格书 - 图文
