FPGA可编程逻辑器件芯片EP4SGX290KF40C3N中文规格书 - 图文

Each Half Block has its own signa and signb signal. Therefore, all of the dataA inputs feeding the same DSP Half Block must have the same sign representation. Similarly, all of the dataB inputs feeding the same DSP Half Block must have the same sign representation. The multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18x18 loopback and Two-Multiplier Adder modes. Refer to “Two-Multiplier Adder Sum Mode” on page5–21 for details.1

When the signa and signb signals are unused, the QuartusII software sets the multiplier to perform unsigned multiplication by default.

The outputs of the multipliers are the only outputs that can feed into the first-stage adder, as shown in Figure5–6. There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder block has the ability to perform addition and subtraction. The control signal for addition or subtraction is static and has to be configured upon compile time. The first-stage adders are used by the sum modes to compute the sum of two multipliers, 18×18-complex multipliers, and to perform the first stage of a 36×36 multiply and shift operation.

Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, round and saturation unit, or the output registers.

Pipeline Register Stage

The output from the first-stage adder can either feed or bypass the pipeline registers, as shown in Figure5–6. Pipeline registers increase the DSP block’s maximum performance (at the expense of extra cycles of latency), especially when using the subsequent DSP block stages. Pipeline registers split up the long signal path between the input-registers/multiplier/first-stage adder and the second-stage

adder/round-and-saturation/output-registers, creating two shorter paths.

Second-Stage Adder

There are four individual 44-bit second-stage adders per DSP block (2adders per half DSP block). You can configure the second-stage adders as follows:

■■■■

The final stage of a 36-bit multiplierA sum of four (18×18)

An accumulator (44-bits maximum)

A chained output summation (44-bits maximum)

111

The chained-output adder can be used at the same time as a second-level adder in chained output summation mode.

The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register.

You cannot use the second-stage adder independently from the multiplier and first-stage adder.

Stratix III Device Handbook, Volume 1

Stratix III Device Handbook, Volume 1Figure8–20.StratixIII IOE Input Registers(Note1)

Notes to Figure8–20:

(1)You can bypass each register block in this path.

(2)This is the 0-phase resynchronization clock (from the read-leveling delay chain).

(3)The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.(4)This input clock comes from the CQn logic block.

(5)This resynchronization clock can come either from the PLL or from the read-leveling delay chain.

(6)The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock, the I/O clock divider can also be fed by the DQS bus or CQn bus.(7)The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.

(8)You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout.

(9)

You must invert the strobe signal needs for DDR, DDR2, and DDR3 interfaces, except for QDR II or QDR II+ SRAM interfaces. This inversion is automatically done if you use the Altera external memory interface IPs.

(10)Each divider feeds up to six pins (from a ×4 DQS group) in the device. To feed wider DQS groups, you must chain multiple clock dividers together by feeding the slaveout output of one divider to the

masterin input of the neighboring pins’ divider.

(11)The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/ synchronization register to feed dataout.Chapter 8:StratixIII External Memory Interface FeaturesExternal Memory Interfaces in StratixIII DevicesChapter 8:External Memory Interfaces in StratixIII DevicesStratixIII External Memory Interface Features

Stratix III Device Handbook, Volume 1

Stratix III Device Handbook, Volume 1Figure8–21.StratixIII IOE Output and Output-Enable Path Registers (Note1)

Half Data Rate to Single Data Rate Output-Enable RegistersFrom Core (2)Alignment Registers (4)DQDouble Data Rate Output-Enable RegistersDFFDFF0DQ1DQDQDQDFFFrom Core (2)DFFDQDQOE Reg ADFFOEOR21DFFDFF0DFFDQ Half Data Rate to Single Data Rate Output RegistersAlignment Registers (4)OE Reg BOEFrom Core (wdata0)(2)DQDouble Data Rate Output RegistersDFFDFF0Q1DQDDQDQTRIFrom Core (wdata1)(2)DFFDQDQDFF1DQ or DQSOutput Reg Ao0DFFDFFDFFDFFDQDQFrom Core (wdata2)(2)DQDFFOutput Reg BoDFF01DQDQFrom Core (wdata3)(2)DFFDQDQDFFDFFDFFHalf-Rate Clock(3)WriteAlignmentClock(5)Clock(3)Notes to Figure8–21:(1)You can bypass each register block of the output and output-enable paths.

(2)Data coming from the FPGA core are at half the frequency of the memory interface.(3)Half-rate and alignment clocks come from the PLL.

(4)These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.

(5)

The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.

Chapter 8:StratixIII External Memory Interface FeaturesExternal Memory Interfaces in StratixIII DevicesChapter 8:External Memory Interfaces in StratixIII DevicesStratixIII External Memory Interface Features

OCT

StratixIII devices feature dynamic calibrated OCT, in which series termination (OCT RS) is turned on when driving signals and turned off when receiving signals, while the parallel termination (OCT RT) is turned off when driving signals and turned on when receiving signals. This feature complements the DDR3/DDR2 SDRAM on-die

termination (ODT), whereby memory termination is turned off when the memory is sending data and turned on when receiving data. You can also use OCT for other memory interfaces to improve signal integrity.1

You cannot use the programmable drive strength and programmable slew rate features when using OCT RS.

To use dynamic calibrated OCT, you must use the RUP and RDN pins to calibrate the OCT calibration block. You can use one OCT calibration block to calibrate one type of termination with the same VCCIO on the entire device. There are up to ten OCT

calibration blocks to allow for different types of terminations throughout the device. For more information, refer to “Dynamic OCT Control” on page8–33.1

You have the option to use the OCT RS feature with or without calibration. However, the OCT RT feature is only available with calibration.

You can also use the RUP and RDN pins as DQ pins. However, you cannot use the ×4 DQS/DQ groups where the RUP and RDN pins are located if you are planning to use dynamic calibrated OCT. The RUP and RDN pins are located in the first and last ×4 DQS/DQ group on each side of the device.

Use the OCT RT/RS setting for uni-directional read and write data; use a dynamic OCT setting for bi-directional data signals.

Programmable IOE Delay Chains

You can use programmable delay chains in the StratixIII I/O registers as deskewing circuitry. Each pin can have a different input delay from the pin to input register or a delay from the output register to the output pin to ensure that the bus has the same delay going into or out of the FPGA. This feature helps read and write time margins as it minimizes the uncertainties between signals in the bus. 1

Deskewing circuitry and programmable IOE delay chains are the same circuit.

Programmable Output Buffer Delay

In addition to allowing output buffer duty cycle adjustment, the programmable output buffer delay chain allows you to adjust the delays between data bits in your output bus to introduce or compensate channel-to-channel skew. Incorporating skew to the output bus helps to minimize simultaneous switching events by enabling smaller parts of the bus to switch simultaneously, instead of the whole bus. This feature is particularly useful in DDR3 SDRAM interfaces where the memory system clock delay can be much larger than the data and data clock/strobe delay. Use this delay chain to add delay to the data and data clock/strobe to better match the memory system clock delay.

Stratix III Device Handbook, Volume 1