Preface
About This Guide
Guide Contents
This manual contains the following chapters:??????????
Chapter1, Configuration OverviewChapter2, Configuration Interface Basics
Chapter3, Boundary-Scan and JTAG ConfigurationChapter4, User PrimitivesChapter5, Configuration Details
Chapter6, Readback and Configuration VerificationChapter7, Reconfiguration and MultiBootChapter8, Readback CRC
Chapter9, Advanced Configuration InterfacesChapter10, Advanced JTAG Configurations
Additional Documentation
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Spartan-6 Family Overview
This overview outlines the features and product selection of the Spartan-6 family.Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for theSpartan-6 family.?
Spartan-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximumI/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, andthermal specifications.?
Spartan-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO? resources available in all Spartan-6 devices.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Preface:About This Guide
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Serial Configuration Interface
2.3.4.
DOUT should be connected to the DIN of the downstream FPGA for daisy-chainedconfiguration modes.
The CCLK net requires Thevenin parallel termination. For more details, see BoardLayout for Configuration Clock (CCLK), page56.
The DONE pin is by default an open-drain output with an internal pull-up. Anadditional external pull-up is recommended. The DONE pin has a programmableactive driver that can be enabled via the BitGen option -g DriveDone.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrecommended.
The SPI control pins, CSO_B and MOSI, toggle during serial configuration.VFS is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is used foreFUSE programming. See eFUSE, page93 for more details.
VBATT is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is the powersource for AES key storage. If AES encryption is unused, VBATT can be tied to eitherVCCAUX or ground, or left unconnected.
If VCCO_2 is 1.8V, VCCAUX must be 2.5V. If VCCO_2 is 2.5V or 3.3V, VCCAUX can beeither 2.5V or 3.3V.
5.6.7.8.
9.
10.The SUSPEND pin should be Low during power up and configuration. If the Suspend
feature is not used, the SUSPEND pin must be connected to ground.
Serial Configuration Data Timing
Figure2-4 shows how configuration data is clocked into Spartan-6 devices in Slave Serial and Master Serial modes.
X-Ref Target - Figure 2-4PROGRAM_BINIT_BMaster CLK begins hereCCLKMaster DINBIT 0BIT 1BIT nBIT n+1Master DOUTData bits clocked out on falling edge of CCLKDONEUG380_c2_04_0121012Figure 2-4:
Notes relevant to Figure2-4:1.2.3.
Serial Configuration Clocking Sequence
Bit 0 represents the MSB of the first byte. For example, if the first byte is 0xAA(1010_1010), bit 0=1, bit 1=0, bit 2=1, etc.
For Master configuration mode, CCLK does not transition until after the Mode pins are sampled, as indicated by the arrow.
CCLK can be free-running in Slave Serial mode.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 2:Configuration Interface Basics
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
SelectMAP Configuration Interface
X-Ref Target - Figure 2-10(4)(5)(6)CCLK(3)CSI_B(2)RDWR_B(1)DATA[0:n]Byte 0Byte 1Byte nUG380_c2_10_042909Figure 2-10:Non-Continuous SelectMAP Data Loading with Controlled CCLK
Notes relevant to Figure2-10:1.2.3.4.5.6.
The Data pins are in the High-Z state while CSI_B is deasserted. The data bus can be x8or x16.
RDWR_B has no effect on the device while CSI_B is deasserted.
CSI_B is asserted by the user. The device begins loading configuration data on risingCCLK edges.
A byte is loaded on the rising CCLK edge.A byte is loaded on the rising CCLK edge.A byte is loaded on the rising CCLK edge.
SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.
In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 modes, see Parallel Bus Bit Order, page81. This convention can be a source of confusion when designing custom configuration solutions. Table2-4 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-4:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle
12
Notes:
1.D[0:7] represent the SelectMAP DATA pins.
Hex Equivalent
0xAB0xCD
D011
D101
D210
D300
D411
D501
D610
D711
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see Configuration Data File Formats, page77).
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2S150-6FG456C中文规格书 - 图文
