Byte Peripheral Interface Parallel Flash Mode
Byte Peripheral Interface Parallel Flash Mode
In BPI-Up (M[2:0]=010) or BPI-Down (M[2:0]=011) mode, the Virtex-5 FPGA configures itself from an industry-standard parallel NOR Flash PROM, as illustrated in Figure2-22. The FPGA drives up to 26 address lines to access the attached parallel Flash. For
configuration, only async read mode is used, where the FPGA drives the address bus, and the Flash PROM drives back the bitstream data. Bus widths of x8 and x16 are supported. Bus widths are auto detected, as described in “Bus Width Auto Detection.” Refer to DS617, Platform Flash XL High-Density Configuration and Storage Device data sheet for the BPI-compatible Flash device from Xilinx.
In BPI modes, the CCLK output is not connected to the BPI Flash device. However, Flash data is still sampled on the rising edge of CCLK. The CCLK output is driven during the BPI modes and therefore must receive the same parallel termination as in the other Master modes. See “Board Layout for Configuration Clock (CCLK),” page73. The timing parameters related to BPI use CCLK as a reference. Virtex-5 BPI modes also support asynchronous page-mode reads to allow an increase in the CCLK frequency. See “Page Mode Support,” page71 for details.
In the BPI-Up mode, the address starts at 0 and increments by 1 until the DONE pin is asserted. If the address reaches the maximum value (26’h3FFFFFF) and configuration is not done (DONE is not asserted), an error flag is raised in the status register, and fallback reconfiguration starts. See “Fallback MultiBoot,” page153.
In the BPI-Down mode, the address start at 26’h3FFFFFF and decrements by 1 until the DONE pin is asserted. If the address reaches the bottom (26’h0), and configuration is still not done (DONE is not asserted), an error flag is raised in the status register and fallback reconfiguration starts. See “Fallback MultiBoot,” page153.
4.7 kΩVirtex-5 FPGAINIT_BPROGRAM_BHSWAPENDONECCLKRS[1:0]FCS_BFOE_BFWE_BADDR[25:0]330ΩBPI FlashCS_BOE_BWE_BADDR[25:0]M[2:0]D[15:0]D[15:0]Note: The BPI Flash vendor data sheet should be referred to for details on the specific Flash signal connectivity.
To prevent address misalignment, close attention should be paid to the Flash family address LSB for the byte/word mode used. Not all Flash families use the A0 as the address LSB.
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Figure 2-22:Virtex-5 BPI Configuration Interface
Additional notes related to Figure2-22:??
M[2:0]=010 for BPI-Up mode and M[2:0]=011 for BPI-Down mode.
Figure2-22 shows the x16 BPI interface. For x8 BPI interfaces, only D[7:0] are used.See “Bus Width Auto Detection.”
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Chapter 2:Configuration Interfaces
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Sending a bitstream to the data pin follows the same bit-swapping rule as inSelectMAP mode. See “Parallel Bus Bit Order.”
If Flash programming is not required, FCS_B, FOE_B, and FWE_B can be tied off; thatis, DONE is connected to FCS_B, FOE_B is tied Low, and FWE_B is tied High.The CCLK outputs are not used to connect to Flash but are used to sample Flash readdata during configuration. All timings are referenced to CCLK. The CCLK pin mustnot be driven or tied High or Low.
The RS[1:0] pins are not connected as shown in Figure2-22. These output pins areonly required for MultiBoot configuration. See Chapter8, “Reconfiguration andMultiBoot.”
HSWAPEN must be connected to either disable or enable the pull-up resistors.If HSWAPEN is left unconnected or tied High, a pull-up resistor is required forFCS_B.
If HSWAPEN is tied Low, the FCB_B, FOE_B, FWE_B, and the address pins haveinternal weak pull-up resistors during configuration. After configuration, FCS_B canbe either controlled by I/O in user mode or by enabling a weak pull-up resistorthrough constraints.
To enable the active driver on DONE, the DriveDONE option in BitGen must beenabled.
“MultiBoot Bitstream Spacing,” page155 provides information on when DCI or DCMlock wait is turned on.
For daisy chaining FPGAs in BPI mode, see Figure2-12, page52.
The BPI Flash vendor data sheet should be referred to for details on the specific Flashsignal connectivity. To prevent address misalignment, close attention should be paidto the Flash family address LSB for the byte/word mode used. Not all Flash familiesuse the A0 as the address LSB.
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Table2-9 defines the BPI configuration interface pins.
If the FPGA is subject to reprogramming or fallback during configuration from the BPI flash, then the INIT pin can be connected to the BPI reset to set the BPI into a known state.
Table 2-9:
Virtex-5 Device BPI Configuration Interface Pins
Type Input
Dedicated or Dual-Purpose
010 = BPI-Up mode011 = BPI-Down mode
HSWAPEN
Input
Dedicated
Controls I/O (except Bank 0 dedicated I/Os) pull-up resistors during configuration. This pin has a built-in weak pull-up resistor.0 = Pull-up during configuration1 = 3-state during configuration
DONE
Bidirectional, Dedicated Active-High signal indicating configuration is complete: Open-Drain, 0 = FPGA not configured or Active
1 = FPGA configured
Description
Pin Name M[2:0]
Dedicated The Mode pins determine the BPI mode:
Virtex-5 FPGA Configuration Guide
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Board Layout for Configuration Clock (CCLK)
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
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Chapter 4:User Primitives
CAPTURE_VIRTEX5
The CAPTURE_VIRTEX5 primitive is used to capture I/O, CLB, and block RAM output flip-flop status, and then read back through the configuration interface. The CAP input is sampled by CLK to generate an internal gcap signal. The I/O and CLB flip-flop status are captured into an FPGA configuration memory cell when the gcap signal is High. There are operation modes, a one-shot mode, or a continuous mode.
In one-shot mode, after the first CAP falling edge, gcap is held to 0 to avoid further capturing. An explicit RCAP command is required to re-arm the capture circuit.In continuous mode, the CAP input is simply sampled by CLK, and becomes the gcap signal, allowing the user to control when to capture.
CAPTURE_VIRTEX5 should not operate simultaneously with the FRAME_ECC_VIRTEX5 primitive or the Readback CRC function (see Chapter9, “Readback CRC”) because capturing a value into configuration memory might cause a false error.Table 4-2:CAPTURE_VIRTEX5 Pin TablePin Name CLKCAP
TypeInputInput
Description
Clock for sampling the CAP input.
Active-High capture enable. The CAP input is sampled by the rising edge of CLK.
ICAP_VIRTEX5
The ICAP_VIRTEX5 primitive works the same way as the SelectMAP configuration
interface except it is on the fabric side, and ICAP has a separate read/write bus, as opposed to the bidirectional bus in SelectMAP. The general SelectMAP timing diagrams and the SelectMAP bitstream ordering information as described in the “SelectMAP Configuration Interface” section of this user guide are also applicable to ICAP. It allows the user to access configuration registers, readback configuration data, or partially reconfigure the FPGA after configuration is done.
ICAP has three data width selections through the ICAP WIDTH parameter: x8, x16, and x32.
The two ICAP ports cannot be operated simultaneously. The design must start from the top ICAP, then switch back and forth between the two. Table 4-3:ICAP_VIRTEX5 Pin TablePin Name CLKCEWRITEI[31:0]
TypeInputInputInputInput
ICAP interface clock
Active-Low ICAP interface select. Equivalent to CS_B in the SelectMAP interface.
0=WRITE, 1=READ. Equivalent to the RDWR_B signal in the SelectMAP interface.
ICAP write data bus. The bus width depends on
ICAP_WIDTH parameter. The bit ordering is identical to the SelectMAP interface. See SelectMap Data Ordering in Figure2-19.
Description
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S100E-7FTG256I中文规格书 - 图文
